# Copyright (C) 2018  Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions 
# and other software and tools, and its AMPP partner logic 
# functions, and any output files from any of the foregoing 
# (including device programming or simulation files), and any 
# associated documentation or information are expressly subject 
# to the terms and conditions of the Intel Program License 
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel FPGA IP License Agreement, or other applicable license
# agreement, including, without limitation, that your use is for
# the sole purpose of programming logic devices manufactured by
# Intel and sold by Intel or its authorized distributors.  Please
# refer to the applicable agreement for further details.


# ***************************************************************************
# ***************************************************************************
# 
# File:		D:/Project/AMBA_BUS/AHB_GEN_201/work/AHB_GEN_dump_all_vcd_nodes.tcl
# 
# Description:	Script for QuestaSim (Verilog) VCD File Dumping
# 		This script is used to direct QuestaSim (Verilog) to dump
# 		all nodes in the design to a VCD output file
# 
# Usages:	D:/Project/AMBA_BUS/AHB_GEN_201/work/AHB_GEN_dump_all_vcd_nodes.tcl
# 
# Generated by:	Quartus Prime
# 		Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition
# 
# Date:		Sat Dec 12 17:34:27 2020
# 
# Design:	AHB_GEN
# 
# ***************************************************************************
# ***************************************************************************

# ----------------------------------------------------------------
#
proc add_vcd_signals { hierarchy vcd_filename } {
#
# Description:	This function directs QuestaSim (Verilog) to print out the
#		appropriate VCD signals, with the hierarchy level
#		prepended to each signal name
#
# ----------------------------------------------------------------

   catch { vcd add "$hierarchy/hclk" }
   catch { vcd add "$hierarchy/hreset_n" }
}

# ----------------------------------------------------------------
#
proc main { argv } {
#
# Description:	Main entry point to script.  Iterate over all
#		hierarchy levels specified, and direct QuestaSim (Verilog)
#		to print the relevant signals under each level
#
# ----------------------------------------------------------------

   set vcd_filename "AHB_GEN.vcd"
   set hierarchy "AHB_GEN"

   vcd file "$vcd_filename"
   vcd on

   add_vcd_signals $hierarchy $vcd_filename
}

main $argv
